1. Field of the Invention
The present invention relates to a ready signal control apparatus connected between a central processing unit (CPU) and a plurality of peripheral circuits which require a wait state of the CPU.
2. Description of the Related Art
Generally, in a computer system, there are two kinds of peripheral circuits: a first type which can operate at a high speed to require no wait state of a CPU, and a second type which can operate at a low speed to require a wait state of the CPU.
In a prior art computer system having a CPU and peripheral circuits of the second type, when the CPU accesses one of the peripheral circuits, the CPU enables a control circuit to generate a selection signal and transmit it to the corresponding peripheral circuit. In response to the selection signal, the corresponding peripheral circuit generates a ready signal which is also called an acknowledgement signal and transmits it to the CPU. As a result, the CPU enters a wait state to access the corresponding peripheral circuit.
In the above-mentioned prior art computer system, however, when the corresponding peripheral circuit is in a fault state for some reason, so that the ready signal never becomes inactive, the CPU continues to be in a wait state for the corresponding peripheral circuit. That is, the CPU substantially becomes in a halt state, and therefore, the CPU cannot access the other peripheral circuits. This will be explained later in detail.